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• Scripting toolÀ» »ç¿ëÇÏ¿© ±âÁ¸ RTL ºí·Ï°ú °ËÁõ ȯ°æÀ» À¯Áö ¹× Çâ»ó
• Software development team°ú Çù¾÷
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• ´ëÁ¹ Çлç ÀÌ»ó
• °æ·Â 5³âÂ÷ ÀÌ»ó
• ASIC/SOC/FPGA °³¹ß °æÇè
• Verilog HDL ¹× C/C+¸¦ »ç¿ëÇÑ ¼³°è/°ËÁõ¿¡ ´ëÇÑ Àü¹® Áö½Ä
• AMBA AXI¿Í memory sub-system¿¡ ´ëÇÑ Áö½Ä
• RTL simulation, debugging, synthesis, and lint/CDCÀ» À§ÇÑ EDA ÅøÀÇ ±â¼ú º¸À¯
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- memory sub-system
- image signal processing
- video codec
• Python/Perl »ç¿ë °¡´ÉÀÚ
• SystemVerilog¸¦ »ç¿ëÇÑ test bench °¡´ÉÀÚ
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